1. Field of the Invention
The invention relates generally to an impedance design method, and more particularly, to an impedance design method for a power network of a chipset.
2. Description of the Related Art
FIG. 1 depicts a diagram of a power network. The power network has N input/output (I/O) ports connected to a power supply Vcc. Ideally, the voltages V1 to VN should all be equal to the power supply Vcc and should never change. In practice, however, a voltage of any I/O port may vary slightly as the current of other I/O ports changes. Take the I/O port 1 as an example, the variation of the current for any other I/O ports 2 through N may result in a slight voltage variation on the I/O port 1.
The problem is caused by the impedances between I/O ports.